DSPMUL SPEC SHEET
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DSPMUL
| DSPMUL -- click for large photo |
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Not recommended for new designs.
DSPMUL DSP Coprocessor Features
• Up to 4 50 MHz Agere DSP32C's
• 1 MByte of SRAM memory per CPU
• 1 DSP32C serial port per CPU
• Requires PC ISA bus slot
• Application software with source
• Price $1300
• Specs Table
• Options Table
Product Description
The DSPMUL coprocessor board features multiple Agere DSP32C chips
each of which offers 50 MHz, 25 Mflop floating point power with 24
bit address and 32 bit data buses for speed and accuracy.
The DSPMUL uses a 16 bit ISA bus interface to the DSP32C PIO that
allows all of the on board memory to be accessed by the PC
while the DSP32C is executing. CPU selection is under program
control. The DSPMUL can be populated with up to 4 CPUs and 1 MB of
SRAM memory per CPU. It includes a high speed serial interface for
each CPU. The serial interfaces are not plain RS232, but are instead
high speed serial connections to the DSP32C for interfacing with
codecs and other serial I/O devices. A complete software package is
also included so you have everything you need to begin developing
applications immediately.
All the software you need to develop stand alone or integrated PC
DSP32C applications comes with the board. This software includes an
assembler, full screen symbolic monitor/debugger, C callable math
library, and many graded examples to help you get started. Source
code for the entire system is included and provides a base for
developing custom applications. The PDF user manual includes
circuit diagrams.
For additional information see:
Manual Excerpts,
Software,
DSPSMT
Specifications Table
| DSPMUL Specs |
| Recommended For: |
Multiple CPU applications |
| Memory: |
One 0ws SRAM ZIP module per CPU, 64 Kb or 1MB size |
| Memory Socket: |
Flush mount machine pin |
| Serial Interface: |
Three-wire 16 Mb/s, 1 per CPU |
| DSP32C Interrupt Pins: |
Available on header |
| CPU: |
Agere DSP32C |
| CPU Speed: |
50 MHz, 25 Mflop |
| CPU Registers: |
21 general purpose integer |
| CPU Accumulators: |
Four 40 bit floating point |
| CPU Internal SRAM: |
6 Kb, 0 wait state |
| CPU ROM: |
none, DSP32C programmed from PC |
| Bus: |
ISA, requires PC/AT slot |
| PC Interface: |
16 bit PC/AT to PIO controller + memory |
| Base Address: |
32 bytes in PC I/O space, DIP switch selectable |
| CPU Select Address: |
4 bytes in PC I/O space, DIP switch selectable |
| Data Transfer Rate: |
3 MB/s via insw/outsw |
| Board Layers: |
6 including separate power and ground planes |
| Board Dimensions: |
Full length XT (4 1/4" x 13 1/4") |
| Supported OS: |
WinNT 4.0, Win95/98, DOS, Linux |
| Price: |
$1300 |
Options Table
Some users may want to consider these additional options.
Option prices vary with market conditions, please call for current price.
| DSPMUL Options |
| Option |
Description |
Price |
| CPU-DSP32C |
Add up to three additional CPUs to the
1 CPU already included with the DSPMUL |
Please Call |
| SRAM-ZIP-1024 |
Add up to 1 additional MB of memory for each
additional CPU to the 1 CPU with 1 MB
already included with the DSPMUL |
Please Call |
|